Microelectronic assemblies generally include one or more ICs, such as for example one or more packaged dies (“chips”) or one or more dies. One or more of such ICs may be mounted on a circuit platform, such as a wafer such as in wafer-level-packaging (“WLP”), printed board (“PB”), a printed wiring board (“PWB”), a printed circuit board (“PCB”), a printed wiring assembly (“PWA”), a printed circuit assembly (“PCA”), a package substrate, an interposer, or a chip carrier. Additionally, one IC may be mounted on another IC. An interposer may be a passive or an active IC, where the latter includes one or more active devices, such as transistors for example, and the former does not include any active device but may include one or more passive devices, such as capacitors, inductors, and/or resistors. Furthermore, an interposer may be formed like a PWB, namely without any circuit elements, such as without any passive or active devices. Additionally, an interposer may include at least one through-substrate-via.
An IC may include conductive elements, such as pathways, traces, tracks, vias, contacts, pads such as contact pads and bond pads, plugs, nodes, or terminals for example, that may be used for making electrical interconnections with a circuit platform. These arrangements may facilitate electrical connections used to provide functionality of ICs. An IC may be coupled to a circuit platform by bonding, such as bonding traces or terminals, for example, of such circuit platform to bond pads or exposed ends of pins or posts or the like of an IC; or an IC may be coupled to a circuit platform by soldering. Additionally, a redistribution layer (“RDL”) may be part of an IC to facilitate a flip-chip configuration, die stacking, or more convenient or accessible position of bond pads for example.
Some passive or active microelectronic devices may be used in a System-in-Package (“SiP”) or other multi-die/component package. However, some SiPs may take up too much area for some applications. Moreover, for some low-profile applications, some SiPs may be used; however, forming a SiP for stacking using through substrate vias may be too expensive for some applications.
Accordingly, it would be desirable and useful to provide vertical integration for a SiP.